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preliminary: the specifications of this device are subject to change without notice. please contact your nearest hitachi? sales dept. regarding specifications. hm5425161b series HM5425801B series hm5425401b series 256m sstl_2 interface ddr sdram 143 mhz/133 mhz/125 mhz/100 mhz 4-mword 16-bit 4-bank/8-mword 8-bit 4-bank/ 16-mword 4-bit 4-bank ade-203-1077 (z) preliminary rev. 0.0 jun. 28, 1999 description the hm54 25161b, the hm54 25801b and the hm54 25401b are the double data rate (ddr) sdram devices. read and write operations are performed at the cross points of the clk and the clk . this high speed data transfer is realized by the 2-bit prefetch piplined architecture. data strobe (dqs) both for read and write are available for high speed and reliable data bus design. by setting extended mode resistor, the on-chip delay locked loop (dll) can be set enable or disable. features jedec standard compatible devices 2.5 v power supply sstl-2 interface for all inputs and outputs clock frequency: 143 mhz/133 mhz/125 mhz/100 mhz data inputs, outputs, and dm are synchronized with dqs 4 banks can operate simultaneously and independently burst read/write operation programmable burst length: 2/4/8 ? burst read stop capability programmable burst sequence ? sequential ? interleave
hm5425161b, HM5425801B, hm5425401b series 2 start addressing capability ? even and odd programmable cas latency: 2/2.5 8192 refresh cycles: 7.8 m s (8192 row/64 ms) 2 variations of refresh ? auto refresh ? self refresh ordering information type no. frequency package hm5425161btt-75a hm5425161btt-75b hm5425161btt-10 143 mhz/133 mhz 133 mhz/100 mhz 125 mhz/100 mhz 400-mill 66-pin plastic tsop ii (ttp-66d) HM5425801Btt-75a HM5425801Btt-75b HM5425801Btt-10 143 mhz/133 mhz 133 mhz/100 mhz 125 mhz/100 mhz hm5425401btt-75a hm5425401btt-75b hm5425401btt-10 143 mhz/133 mhz 133 mhz/100 mhz 125 mhz/100 mhz
hm5425161b, HM5425801B, hm5425401b series 3 pin arrangement (hm5425161b) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 v cc dq0 v ccq dq1 dq2 v ssq dq3 dq4 v ccq dq5 dq6 v ssq dq7 nc v ccq dqsl nc v cc nc dml we cas ras cs nc a14 a13 a10/ap a0 a1 a2 a3 v cc v ss dq15 v ssq dq14 dq13 v ccq dq12 dq11 v ssq dq10 dq9 v ccq dq8 nc v ssq dqsu nc v ref v ss dmu clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 66-pin tsop (top view)
hm5425161b, HM5425801B, hm5425401b series 4 pin description pin name function a0 to a14 address input ? row address a0 to a12 ? column address a0 to a8 ? bank select address a13 (ba1)/a14 (ba0) dq0 to dq15 data-input/output dqsu upper input and output data strobe dqsl lower input and output data strobe cs chip select ras row address strobe command cas column address strobe command we write enable dmu upper byte input mask dml lower byte input mask clk clock input clk differential clock input cke clock enable v ref input reference voltage v cc power for internal circuit v ss ground for internal circuit v ccq power for dq circuit v ssq ground for dq circuit nc no connection
hm5425161b, HM5425801B, hm5425401b series 5 pin arrangement (HM5425801B) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 v cc dq0 v ccq nc dq1 v ssq nc dq2 v ccq nc dq3 v ssq nc nc v ccq nc nc v cc nc nc we cas ras cs nc a14 a13 a10/ap a0 a1 a2 a3 v cc v ss dq7 v ssq nc dq6 v ccq nc dq5 v ssq nc dq4 v ccq nc nc v ssq dqs nc v ref v ss dm clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 66-pin tsop (top view)
hm5425161b, HM5425801B, hm5425401b series 6 pin description pin name function a0 to a14 address input ? row address a0 to a12 ? column address a0 to a9 ? bank select address a13 (ba1)/a14 (ba0) dq0 to dq7 data-input/output dqs input and output data strobe cs chip select ras row address strobe command cas column address strobe command we write enable dm input mask clk clock input clk differential clock input cke clock enable v ref input reference voltage v cc power for internal circuit v ss ground for internal circuit v ccq power for dq circuit v ssq ground for dq circuit nc no connection
hm5425161b, HM5425801B, hm5425401b series 7 pin arrangement (hm5425401b) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 v cc nc v ccq nc dq0 v ssq nc nc v ccq nc dq1 v ssq nc nc v ccq nc nc v cc nc nc we cas ras cs nc a14 a13 a10/ap a0 a1 a2 a3 v cc v ss nc v ssq nc dq3 v ccq nc nc v ssq nc dq2 v ccq nc nc v ssq dqs nc v ref v ss dm clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 66-pin tsop (top view)
hm5425161b, HM5425801B, hm5425401b series 8 pin description pin name function a0 to a14 address input ? row address a0 to a12 ? column address a0 to a9, a11 ? bank select address a13 (ba1)/a14 (ba0) dq0 to dq3 data-input/output dqs output data strobe cs chip select ras row address strobe command cas column address strobe command we write enable dm input mask clk clock input clk differential clock input cke clock enable v ref input reference voltage v cc power for internal circuit v ss ground for internal circuit v ccq power for dq circuit v ssq ground for dq circuit nc no connection
hm5425161b, HM5425801B, hm5425401b series 9 block diagram column address counter column address buffer row address buffer bank select refresh counter address register address (a0 to a14) ay0 to ay11 ax0 to ax12 ax13, ax14 a0 to a14 dq* 2 input buffer output buffer dqs buffer row decoder sense amplifier & i/o bus column decoder bank 0 * 1 * 1 * 1 * 1 notes: 1. 8192 row 512 column 16 bit: hm5425161b 8192 row 1024 column 8 bit: HM5425801B 8192 row 2048 column 4 bit: hm5425401b 2. dq0 to dq15: hm5425161b dq0 to dq7: HM5425801B dq0 to dq3: hm5425401b row decoder sense amplifier & i/o bus column decoder bank 1 row decoder sense amplifier & i/o bus column decoder bank 2 row decoder clk cke dm, dmu/dml dll dqs, dqsu/dqsl clk ras cas we cs sense amplifier & i/o bus column decoder bank 3 control logic & timing generator mode register
hm5425161b, HM5425801B, hm5425401b series 10 pin functions (1) clk, clk (input pin): the clk and the clk are the master clock inputs. all inputs except dms, dqss and dqs are referred to the cross point of the clk rising edge and the v ref level. when a read operation, dqss and dqs are referred to the cross point of the clk and the clk . when a write operation, dms and dqs are referred to the cross point of the dqs and the v ref level. dqss for write operation are referred to the cross point of the clk and the clk . cs (input pin): when cs is low, commands and data can be input. when cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. ras , cas , and we (input pins): these pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. see "command operation". a0 to a12 (input pins): row address (ax0 to ax12) is determined by the a0 to the a12 level at the cross point of the clk rising edge and the v ref level in a bank active command cycle. column address (ay0 to ay8; the hm5425161b, ay0 to ay9; the HM5425801B, ay0 to ay9, ay11; the hm5425401b) is loaded via the a0 to the a9 at the cross point of the clk rising edge and the v ref level in a read or a write command cycle. this column address becomes the starting address of a burst operation. a10 ( ap) (input pin): a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by a13 (ba1)/a14 (ba0) is precharged. if a10 = high when read or write command, auto-precharge function is enabled. while a10 = low, auto-precharge function is disabled. a13 (ba1)/a14 (ba0) (input pin): a13 (ba1)/a14 (ba0) are bank select signals. the memory array is divided into bank 0, bank 1, bank 2 and bank 3. if a13 = low and a14 = low, bank 0 is selected. if a13 = high and a14 = low, bank 1 is selected. if a13 = low and a14 = high, bank 2 is selected. if a13 = high and a14 = high, bank 3 is selected. cke (input pin): cke controls power down and self-refresh. the power down and the self-refresh commands are entered when the cke is driven low and exited when it resumes to high. the cke level must be kept for 1 clk cycle (= t ckepw ) at least, that is, if cke changes at the cross point of the clk rising edge and the v ref level with proper setup time t is , by the next clk rising edge cke level must be kept with proper hold time t ih .
hm5425161b, HM5425801B, hm5425401b series 11 pin functions (2) dm, dmu/dml (input pins): dm (the hm54 25801b and the hm54 25401b), dm u/dml (the hm5425161b) are the reference signals of the data input mask function. dms are sampled at the cross point of dqs and v ref . dmu/dml provide the byte mask function. when dmu/dml = high, the data input at the same timing are masked while the internal burst counter will be count up. dml controls the lower byte (dq0 to dq7) and dmu controls the upper byte (dq8 to dq15) of write data. dq0 to dq15 (input and output pins): data are input to and output from these pins (the dq0 to the dq15; the hm5425161b, the dq0 to the dq7; the HM5425801B, the dq0 to the dq3; the hm5425401b). dqs, dqsu/dqsl (input and output pin): dqs (the hm54 25801b and the hm54 25401b), dqsu/dqsl (the hm5425161b) provide the read data strobes (as output) and the write data strobes (as input). dqsl is the lower byte (dq0 to dq7) data strobe signal, dqsu is the upper byte (dq8 to dq15) data strobe signal. v cc and v ccq (power supply pins): 2.5 v is applied. (v cc is for the internal circuit and v ccq is for the output buffer.) v ss and v ssq (power supply pins): ground is connected. (v ss is for the internal circuit and v ssq is for the output buffer.)
hm5425161b, HM5425801B, hm5425401b series 12 command operation command truth table the hm5425161b, the hm54 25801b and hm5425401b recognize the following commands specified by the cs , ras , cas , we and address pins. all other combinations than those in the table below are illegal. cke command symbol n ?1 n cs ras cas we ba1 ba0 ap address ignore command desl h h no operation nop h lhhh burst stop in read command bst h lhhl column address and read command read h lhlhvvlv read with auto-precharge reada h lhlhvvhv column address and write command writ h lhllvvlv write with auto-precharge writa h lhllvvhv row address strobe and bank active actv h llhhvvvv precharge select bank pre h llhlvvl precharge all bank pall h llhl h refresh ref h h l l l h self h l l l l h mode register set mrs h lllllllv emrs h lllllhlv notes: 1. h: v ih . l: v il . : v ih or v il . v: valid address input 2. the cke level must be kept for 1 clk cycle (= t ckepw ) at least. ignore command [desl]: when cs is high at the cross point of the clk rising edge and the v ref level, every input are neglected and internal status is held. no operation [nop]: as long as this command is input at the cross point of the clk rising edge and the v ref level, address and data input are neglected and internal status is held. burst stop in read operation [bst]: this command stops a burst read operation, which is not applicable for a burst write operation. column address strobe and read command [read]: this command starts a read operation. the start address of the burst read is determined by the column address (ay0 to ay8; the hm5425161b, ay0 to ay9; the HM5425801B, ay0 to ay9, ay11; the hm54 25401b) and the bank select address (ba). after the completion of the read operation, the output buffer becomes high-z.
hm5425161b, HM5425801B, hm5425401b series 13 read with auto-precharge [reada]: this command starts a read operation. after completion of the read operation, precharge is automatically executed. column address strobe and write command [writ]: this command starts a write operation. the start address of the burst write is determined by the column address (ay0 to ay8; the hm54 25161b, ay0 to ay9; the HM5425801B, ay0 to ay9, ay11; the hm5425401b) and the bank select address (ba). write with auto-precharge [writa]: this command starts a write operation. after completion of the write operation, precharge is automatically executed. row address strobe and bank activate [actv]: this command activates the bank selected by a13/a14 (ba) and determines a row address (ax0 to ax12). when a13 = a14 = low, bank 0 is activated. when a13 = high and a14 = low, bank 1 is activated. when a13 = low and a14 = high, bank 2 is activated. when a13 = a14 = high, bank 3 is activated. precharge selected bank [pre]: this command starts a pre-charge operation for the bank selected by a13/a14. precharge all banks [pall]: this command starts a precharge operation for all banks. refresh [ref/self]: this command starts a refresh operation. there are two types of refresh operation, one is auto-refresh, and another is self-refresh. for details, refer to the cke truth table section. mode register set/extended mode register set [mrs/emrs]: the ddr sdram has the two mode registers, the mode register and the extended mode register, to defines how it works. the both mode registers are set through the address pins (the a0 to the a14) in the mode register set cycle. for details, refer to "mode register and extended mode register set".
hm5425161b, HM5425801B, hm5425401b series 14 cke truth table cke current state command n ?1 n cs ras cas we address notes idle auto-refresh command (ref) h h l l l h 2 idle self-refresh entry (self) h l l l l h 2 idle power down entry (pden) h l l h h h hlh self refresh self refresh exit (selfx) l h l h h h lhh power down power down exit (pdex) l h l h h h lhh notes: 1. h: v ih . l: v il . : v ih or v il . 2. all the banks must be in idle before executing this command. 3. the cke level must be kept for 1 clk cycle (= t ckepw ) at least. auto-refresh command [ref]: this command executes auto-refresh. the banks and the row addresses to be refreshed are internally determined by the internal refresh contoroller. the average refresh cycle is 7.8 m s. the output buffer becomes high-z after auto-refresh start. precharge has been completed automatically after the auto-refresh. the actv or mrs command can be issued t rfc after the last auto-refresh command. self-refresh entry [self]: this command starts self-refresh. the self-refresh operation continues as long as cke is held low. during the self-refresh operation, all row addresses are repeated refreshing by the internal refresh contoroller. a self-refresh is terminated by a self-refresh exit command. power down mode entry [pden]: t pden (= 1 cycle) after the cycle when [pden] is issued. the ddr sdram enters into power-down mode. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. no internal refresh operation occurs during the power down mode. [pden] do not disable dll. self-refresh exit [selfx]: this command is executed to exit from self-refresh mode. 10 cycles (= t snr ) after [selfx], non-read commands can be executed. for read operation, wait for 200 cycles (= t srd ) after [selfx] to adjust dout timing by dll. after the exit, within 7.8 m s input auto-refresh command. power down exit [pdex]: the ddr sdram can exit from power down mode t pdex (1 cycle min.) after the cycle when [pdex] is issued.
hm5425161b, HM5425801B, hm5425401b series 15 function truth table the following tables show the operations that are performed when each command is issued in each state of the ddr sdram. function truth table (1) current state cs ras cas we address command operation next state precharging* 2 h desl nop ldle lhhh nop nop ldle lhhl bst illegal* 12 l h l h ba, ca, a10 read/reada illegal* 12 l h l l ba, ca, a10 writ/writa illegal* 12 l l h h ba, ra actv illegal* 12 l l h l ba, a10 pre, pall nop ldle ll l illegal idle* 3 h desl nop ldle lhhh nop nop ldle lhhl bst illegal* 12 l h l h ba, ca, a10 read/reada illegal* 12 l h l l ba, ca, a10 writ/writa illegal* 12 l l h h ba, ra actv illegal* 12 activating l l h l ba, a10 pre, pall nop ldle ll lh ref, self refresh/ selfrefresh* 13 ldle/ selfrefresh l l l l mode mrs mode register set* 13 ldle refresh (auto-refresh)* 4 h desl nop ldle lhhh nop nop ldle hh hl bst illegal lhl illegal ll illegal
hm5425161b, HM5425801B, hm5425401b series 16 function truth table (2) current state cs ras cas we address command operation next state activating* 5 h desl nop active lhhh nop nop active lhhl bst illegal* 12 l h l h ba, ca, a10 read/reada illegal* 12 l h l l ba, ca, a10 writ/writa illegal* 12 l l h h ba, ra actv illegal* 12 l l h l ba, a10 pre, pall illegal* 12 ll l illegal active* 6 h desl nop active lhhh nop nop active lhhl bst illegal active l h l h ba, ca, a10 read/reada starting read operation read/read a l h l l ba, ca, a10 writ/writa starting write operation write recovering/ precharging l l h h ba, ra actv illegal* 12 l l h l ba, a10 pre, pall pre-charge idle ll l illegal read* 7 h desl nop active lhhh nop nop active lhhl bst bst active lhlh ba, ca, a10 read/reada interrupting burst read operation to start new read active lhll ba, ca, a10 writ/writa illegal* 14 l l h h ba, ra actv illegal* 12 l l h l ba, a10 pre, pall interrupting burst read operation to start pre-charge precharging ll l illegal
hm5425161b, HM5425801B, hm5425401b series 17 function truth table (3) current state cs ras cas we address command operation next state read with auto- pre-charge* 8 h desl nop precharging lhhh nop nop precharging lhhl bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra actv illegal* 12 l l h l ba, a10 pre, pall illegal* 12 ll l illegal write* 9 h desl nop write recovering lhhh nop nop write recovering lhhl bst illegal l h l h ba, ca, a10 read/reada interrupting burst write operation to start read operation. read/reada l h l l ba, ca, a10 writ/writa interrupting burst write operation to start new write operation. write/writea l l h h ba, ra actv illegal* 12 l l h l ba, a10 pre, pall interrupting write operation to start pre-charge. idle ll l illegal write recovering* 10 h desl nop active lhhh nop nop active lhhl bst illegal l h l h ba, ca, a10 read/reada starting read operation. read/reada l h l l ba, ca, a10 writ/writa starting new write operation. write/writea l l h h ba, ra actv illegal* 12 l l h l ba, a10 pre/pall illegal* 12 ll l illegal
hm5425161b, HM5425801B, hm5425401b series 18 function truth table (4) current state cs ras cas we address command operation next state write with auto- pre-charge* 11 h desl nop precharging lhhh nop nop precharging lhhl bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv illegal* 12 l l h l ba, a10 pre, pall illegal* 12 ll l illegal notes: 1. h: v ih . l: v il . : v ih or v il . 2. the ddr sdram is in "precharging" state for t rp after precharge command is issued. 3. the ddr sdram reachs "idle" state t rp after precharge command is issued. 4. the ddr sdram is in "refresh" state for t rc after auto-refresh command is issued. 5. the ddr sdram is in "activating" state for t rcd after actv command is issued. 6. the ddr sdram is in "active" state after "activating" is completed. 7. the ddr sdram is in "read" state until burst data have been output and dq output circuits are turned off. 8. the ddr sdram is in "read with auto-precharge" from reada command until burst data has been output and dq output circuits are turned off. 9. the ddr sdram is in "write" state from writ command to the last burst data are input. 10. the ddr sdram is in "write recovering" for t wr after the last data are input. 11. the ddr sdram is in "write with auto-precharge" until t wr after the last data has been input. 12. this command may be issued for other banks, depending on the state of the banks. 13. all banks must be in "idle". 14. before executing a write command to stop the preceding burst read operation, bst command must be issued.
hm5425161b, HM5425801B, hm5425401b series 19 simplified state diagram precharge row active idle idle power down auto refresh self refresh mode register set active power down power on writea reada sr entry sr exit mrs refresh cke cke_ cke cke_ active write read write with ap read with ap power applied precharge ap read write write with ap read with read with ap write with ap precharge precharge precharge *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
hm5425161b, HM5425801B, hm5425401b series 20 operation of the ddr sdram power-up sequence the following sequence is recommended for power-up. (1) apply power and attempt to maintain cke at an lvcmos low state (all other inputs may be undefined). apply v cc before or at the same time as v ccq . apply v ccq before or at the same time as v tt and v ref . (2) start clock and maintain stable condition for a minimum of 200 m s. (3) after the minimum 200 m s of stable power and clock (clk, clk ), apply nop and take cke high. (4) issue precharge all command for the device. (5) issue emrs to enable dll. (6) issue a mode register set command (mrs) for "dll reset" with bit a8 set to high (an additional 200 cycles of clock input is required to lock the dll after every dll reset). (7) issue precharge all command for the device.* 1 (8) issue 2 or more auto-refresh commands.* 1 (9) issue a mode register set command to initialize device operation. note: 1. sequence of (7) and (8) may be reversed. power-up sequence after cke goes high command emrs pall mrs ref 2 cycles (min) 2 cycles (min) 200 cycles (min) 2 cycles (min) 2 cycles (min) t rp t rc t rc pall mrs ref ref any command dll enable dll reset
hm5425161b, HM5425801B, hm5425401b series 21 mode register and extended mode register set there are two mode registers, the mode register and the extended mode register so as to define the operating mode. parameters are set to both through the a0 to the a14 pins by the mode register set command [mrs] or the extended mode register set command [emrs]. the mode register and the extended mode register are set by inputting signal via the a0 to the a14 during mode register set cycles. a14 (ba0) and a13 (ba1) determine which one of the mode register or the extended mode register are set. prior to a read or a write operation, the mode register must be set. remind that no other parameters are shown in the table bellow are allowed to input to the registers. mode register set [mrs] ( a14 = 0, a13 = 0) a2 a1 a0 burst length 001 2 010 4 011 8 bt=0 bt=1 2 4 8 a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 010 2 2.5 110 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 000 0 dr lmode bt bl a8 0no 1 yes dll reset a11 a10 a12 a13 (ba1) 0 a14 (ba0) 0 mrs extended mode register set [emrs] (a14 = 1, a13 = 0) a0 0 dll enable 1 dll disable dll control a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 00 0 0 00 0 0 0 0 dll 0 a11 a10 a12 a13 (ba1) 0 a14 (ba0) 1 emrs
hm5425161b, HM5425801B, hm5425401b series 22 burst operation the burst type (bt) and the first three bits of the column address determines the order of a data out. a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequence 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequence starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequence starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
hm5425161b, HM5425801B, hm5425401b series 23 read/write operations bank active: a read or a write operation begins with the bank active command [actv]. the bank active command determines a bank address (ax14, ax13) and a row address (ax0 to ax12). for the bank and the row, a read or a write command can be issued t rcd after the actv is issued. read operation: the burst length (bl), the cas latency (cl) and the burst type (bt) of the mode register are referred when a read command is issued. the burst length (bl) determines the length of a sequential output data by the read command which can be set to 2, 4, or 8. the starting address of the burst read is defined by the column address (ay0 to ay8; the hm5425161b, ay0 to ay9; the HM5425801B, ay0 to ay9, ay11; the hm5425401b), the bank select address (ax14, ax13) which are loaded via the a0 to a14 pins in the cycle when the read command is issued. the data output timing are characterized by cl (2 or 2.5) and t ac . the read burst start cl t ck + t ac (ns) after the clock rising edge where the read command are latched. the ddr sdram output the data strobe through dqs or dqsu/dqsl simultaneously with data. t rpre prior to the first rising edge of the data strobe, the dqs or the dqsu/dqsl are driven low from v tt level. this low period of dqs is referred as read preamble. the burst data are output coincidentally at both the rising and falling edge of the data strobe. the dq pins become high-z in the next cycle after the burst read operation completed. t rpst from the last falling edge of the data strobe, the dqs pins become high-z. this low period of dqs is referred as read postamble. read operation (burst length) d0 d1 d0 d1 d2 d3 d0 d1 d2 d3 d4 d5 d6 d7 clk clk address dqs* dout bl = 2 bl = 4 bl = 8 command cas latency = 2 bl: burst length t1 t0 t2 t3 t4 t5 t6 t7 t8 t rcd t rpre dqs*:dqs,dusu/dqsl t rpst actv nop nop nop read ! " row column
hm5425161b, HM5425801B, hm5425401b series 24 read operation ( cas latency) clk clk dqs v tt v tt v tt v tt dq dqs dq cl = 2 cl = 2.5 command t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 d0 d1 d2 d3 d0 d1 d2 d3 t rpst t rpre t rpre t rpst t ac ,t dqsck t ac ,t dqsck read nop
hm5425161b, HM5425801B, hm5425401b series 25 write operation : the burst length (bl) and the burst type (bt) of the mode register are referred when a write command is issued. the burst length (bl) determines the length of a sequential data input by the write command which can be set to 2, 4, or 8. the latency from write command to data input is fixed to 1. the starting address of the burst read is defined by the column address (ay0 to ay8; the hm5425161b, ay0 to ay9; the HM5425801B, ay0 to ay9, ay11; the hm5425401b), the bank select address (ax14, ax13) which are loaded via the a0 to a14 pins in the cycle when the write command is issued. dqs, dqsu/dqsl should be input as the strobe for the input-data and dm, dmu/dml as well during burst operation. t wpreh prior to the first rising edge of the dqs, the dqsu/dqsl should be set to low and t wpst after the last falling edge of the data strobe can be set to h igh-z. the leading low period of dqs is referred as write preamble. the last low period of dqs is referred as wrtie postamble. write operation in1 in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in6 in7 clk clk address dqs* din bl = 2 bl = 4 bl = 8 command bl: burst length t1 t0 t2 t3 t3.5 t4 t5 t6 t7 t8 t rcd t wpst dqs*:dqs,dqsu/dqsl in0 actv nop nop nop write t wpreh t wpres # ! " # row column
hm5425161b, HM5425801B, hm5425401b series 26 burst stop burst stop command during burst read: the burst stop (bst) command is used to stop data output during a burst read. the bst command stops the burst read and sets the output buffer to high-z. t bstz (= cl) cycles after a bst command issued, the dq pins become high-z. the bst command is not supported for the burst write operation. note that bank address is not referred when this command is executed. burst stop during a read operation clk clk dqs dq dqs dq cl = 2 cl = 2.5 command t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 d0 d1 d0 d1 cl: cas latency read bst nop 2 cycles t bstz t bstz 2.5 cycles
hm5425161b, HM5425801B, hm5425401b series 27 auto precharge read with auto-precharge: the precharge is automatically performed after completing a read operation. the precharge starts t rpd (bl/2) cycle after reada command input. t rcd for reada should be determined so that t rc (actv to actv) spec. is obeyed when reada is issued successively after a bank active command, that is t rcd (reada) 3 t rc (min.)-t rp (min.)-t rpd . a column command to the other active bank can be issued the next cycle after the last data output. read with auto-precharge command does not limit row commands execution for other bank. d0 d1 d2 d3 clk clk dq command t ras (min) t rp (min) t rcd (min) actv note: internal auto-precharge starts at the timing indicated by " ". nop 2 cycles (= bl/2) reada actv dqs, dqsu/dqsl t ac ,t dqsck t rpd
hm5425161b, HM5425801B, hm5425401b series 28 write with auto-precharge: the precharge is automatically performed after completing a burst write operation. the precharge operation is started t wpd (= bl/ 2 + 3) cycles after writa command issued. t rcd for writa should be determined so that t rc (actv to actv) spec. is obeyed when writa is issued successively after a bank active command, that is t rcd (writa) 3 t rc (min.)-t rp (min.)-t wpd . a column command to the other active command can be issued the next cycle after the internal precharge command issued. write with auto-precharge command does not limit row commands execution for other bank. burst write (burst length = 4) d1 d2 d3 d4 clk clk dq command dm, dmu/dml t ras (min) t rcd (min) # t rp dqs, dqsu/dqsl actv writa actv bl/2 + 3 cycles t wpd note: internal auto-precharge starts at the timing indicated by " ". burst length = 4 nop nop
hm5425161b, HM5425801B, hm5425401b series 29 command intervals a read command to the consecutive read command interval destination row of the consecutive read command bank address row address state operation 1. same same active the consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. 2. same different precharge the bank to interrupt the preceding read operation. t rp after the precharge command, issue the actv command. t rcd after the actv command, the consecutive read command can be issued. see ? read command to the consecutive precharge interval?section. 3. different any active the consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. idle precharge the bank without interrupting the preceding read operation. t rp after the precharge command, issue the actv command. t rcd after the actv command, the consecutive read command can be issued. read to read command interval (same row address in the same bank) " # a0 a1 b0 b1 b2 b3 clk clk address ba dout dqs, dqsu/dqsl command t1 t0 t2 t3 t4 t5 t6 t7 t8 bank0 active column = a dout column = b dout " # cas latency = 2 burst length = 4 bank0 nop actv nop read row column a read column b column = a read column = b read
hm5425161b, HM5425801B, hm5425401b series 30 read to read command interval (different bank) ! a0 a1 b0 b1 b2 b3 clk clk address ba dout dqs, dqsu/dqsl command t1 t0 t2 t3 t4 t5 t6 t7 t8 t9 bank0 active bank3 active bank0 read bank3 read bank0 dout cas latency = 2 burst length = 4 nop actv nop nop row0 actv read row1 column a read column b column = a read column = b read bank3 dout
hm5425161b, HM5425801B, hm5425401b series 31 a write command to the consecutive write command interval: destination row of the consecutive write command bank address row address state operation 1. same same active the consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. 2. same different precharge the bank to interrupt the preceding write operation. t rp after the precharge command, issue the actv command. t rcd after the actv command, the consecutive write command can be issued. see ? write command to the consecutive precharge interval?section. 3. different any active the consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. idle precharge the bank without interrupting the preceding write operation. t rp after the precharge command, issue the actv command. t rcd after the actv command, the consecutive write command can be issued. write to write command interval (same row address in the same bank) " # ! a0 a1 b0 b1 b2 b3 clk clk address ba din command t1 t0 t2 t3 t4 t5 t6 t7 t8 bank0 active
# ! burst length = 4 bank0 nop dqs, dqsu/dqsl actv nop writ row column a writ column b column = a write column = b write
hm5425161b, HM5425801B, hm5425401b series 32 write to write command interval (different bank) ! " # a0 a1 b0 b1 b2 b3 clk clk address ba din command t1 t0 t2 t3 t4 t5 t6 t7 t8 t9 bank0 active bank3 active bank0 write bank3 write burst length = 4 bank0, 3 nop dqs, dqsu/dqsl actv nop actv writ row0 row1 column a writ column b
hm5425161b, HM5425801B, hm5425401b series 33 a read command to the consecutive write command interval with the bst command destination row of the consecutive write command bank address row address state operation 1. same same active issue the bst command. t bstw ( 3 t bstz ) after the bst command, the consecutive write command can be issued. 2. same different precharge the bank to interrupt the preceding read operation. t rp after the precharge command, issue the actv command. t rcd after the actv command, the consecutive write command can be issued. see ? read command to the consecutive precharge interval?section. 3. different any active issue the bst command. t bstw ( 3 t bstz ) after the bst command, the consecutive write command can be issued. idle precharge the bank independently of the preceding read operation. t rp after the precharge command, issue the actv command. t rcd after the actv command, the consecutive write command can be issued. read to write command interval q0 q1 d0 d1 d2 d3 clk clk dm, dmu/dml dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 ! " # burst length = 4 cas latency= 2 dqs, dqsu/dqsl output input t bstw ( 3 t bstz ) high-z read writ bst nop nop t bstz (= cl)
hm5425161b, HM5425801B, hm5425401b series 34 a write command to the consecutive read command interval: to complete the burst operation destination row of the consecutive read command bank address row address state operation 1. same same active to complete the burst operation, the consecutive read command should be performed t wrd (= bl/ 2 + 2) after the write command. 2. same different precharge the bank t wrd after the preceding write command. t rp after the precharge command, issue the actv command. t rcd after the actv command, the consecutive read command can be issued. see ? read command to the consecutive precharge interval?section. 3. different any active to complete a burst operation, the consecutive read command should be performed t wrd (= bl/ 2 + 2) after the write command. idle precharge the bank independently of the preceding write operation. t rp after the precharge command, issue the actv command. t rcd after the actv command, the consecutive read command can be issued. write to read command interval d0 d1 d2 d3 q2 q0 q1 clk clk dm, dmu/dml dq command t1 t0 t2 t3 t4 t5 t6 ! "
! bl = 4 cl = 2 t wrd (min) dqs, dqsu/dqsl input output bl/2 + 2 cycle writ nop nop read
hm5425161b, HM5425801B, hm5425401b series 35 a write command to the consecutive read command interval: to interrupt the write operation destination row of the consecutive read command bank address row address state operation 1. same same active dm, dmu/dml must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm, dmu/dml is not necessary. 2. same different * 1 3. different any active dm, dmu/dml must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm, dmu/dml is not necessary. idle ? 1 note: 1. precharge must be preceded to read command. therefore read command can not interrupt the write operation in this case. write to read command interval (samebank, same row address) [write to read delay = 1 clock cycle] d0 d1 d2 q0 q1 q2 q3 clk clk dm, dmu/dml dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 ! " # bl = 4 cl= 2 dqs, dqsu/dqsl cl=2 data masked by read command 1 cycle read nop writ high-z high-z
hm5425161b, HM5425801B, hm5425401b series 36 [ write to read delay = 2 clock cycle] d0 d1 d2 d3 q0 q1 q2 q3 clk clk dm, dmu/dml dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl= 2 dqs, dqsu/dqsl cl=2 data masked by read command data masked by dm
! " 2 cycle read nop nop writ high-z high-z [ write to read delay = 3 clock cycle] d0 d1 d2 d3 q0 q1 q2 q3 clk clk dm, dmu/dml dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl= 2 dqs, dqsu/dqsl cl=2 data masked by dm ! "
! " 3 cycle read writ nop nop
hm5425161b, HM5425801B, hm5425401b series 37 a read command to the consecutive precharge command interval (same bank): to output all data: to complete a burst read opeartion and get a burst length of data, the consecutive precharge command must be issued t rpd (= bl/ 2 cycles) after the read command is issued. read to precharge command interval (same bank): to output all data cas latency = 2, burst length = 4 a0 a1 a2 a3 clk clk dout dqs, dqsu/dqsl command t1 t0 t2 t3 t4 t5 t6 t7 t8 t rpd = bl/2 read nop nop nop pre/ pall cas latency = 2.5, burst length = 4 a0 a1 a2 a3 clk clk dout dqs, dqsu/dqsl command t1 t0 t2 t3 t4 t5 t6 t7 t8 t rpd = bl/2 read nop nop nop pre/ pall
hm5425161b, HM5425801B, hm5425401b series 38 read to precharge command interval (same bank): to stop output data a burst data output can be interrupted with a precharge command. all dq pins and dqs pins become high- z t hzp (= cl) after the precharge command. cas latency = 2, burst length = 2, 4, 8 a0 a1 clk clk dout dqs, dqsu/dqsl command t1 t0 t2 t3 t4 t5 t6 t7 t8 pre/pall t hzp = cl + 1 read nop nop high-z high-z cas latency = 2.5, burst length = 2, 4, 8 a0 a1 clk clk dout dqs, dqsu/dqsl command t1 t0 t2 t3 t4 t5 t6 t7 t8 high-z high-z t hzp = cl + 1 cl = 2.5 read nop nop pre/pall
hm5425161b, HM5425801B, hm5425401b series 39 a write command to the consecutive precharge command interval (same bank): the minimum interval t wpd ((bl/ 2 + 3) cycles) is necessary between the write command and the precharge command. write to precharge command interval (same bank) burst length = 4 a0 a1 a2 a3 clk clk din dm, dmu/dml dqs, dqsu/dqsl command t1 t0 t2 t3 t4 t5 t6 t7 last data input t wpd ! "
writ nop nop t wr bl/2 +3 cycles pre/pall
hm5425161b, HM5425801B, hm5425401b series 40 bank active command interval: destination row of the consecutive actv command bank address row address state operation 1. same any active two successive actv commands can be issued at t rc interval. in between two successive actv operations, precharge command should be executed. 2. different any active prechage the bank. t rp after the precharge command, the consecutive actv command can be issued. idle t rrd after an actv command, the next actv command can be issued. bank active to bank active clk clk command ba t rc address
actv t rrd bank0 active bank3 active bank0 precharge bank0 active ! " # pre actv row: 0 nop nop nop actv
actv row: 1 row: 0 mode register set to bank-active command interval: the interval between setting the mode register and executing a bank-active command must be no less than t mrd . clk clk command address nop nop mrs actv t mrd mode register set bank3 active
" code bs and row
hm5425161b, HM5425801B, hm5425401b series 41 dmu/dml control (hm5425161b) dmu can mask upper byte of input data. dml can mask lower byte of input data. by setting dmu/dml to low, data can be written. when dmu/dml is set to high, the corresponding data is not written, and the previous data is held. the latency between dmu/dml input and enabling/disabling mask function is 0. dm control (HM5425801B/hm5425401b) dm can mask input data. by setting dm to low, data can be written. when dm is set to high, the corresponding data is not written, and the previous data is held. the latency between dm input and enabling/disabling mask function is 0. mask mask dqs, dqsu/dqsl dq dm, dmu/dml t1 t2 t3 t4 t5 t6 write mask latency = 0
hm5425161b, HM5425801B, hm5425401b series 42 absolute maximum ratings parameter symbol value unit note voltage on any pin relative to v ss v t ?.0 to +4.6 v 1 supply voltage relative to v ss v cc , v ccq ?.0 to +4.6 v 1 short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg ?5 to +125 c note: 1. refer to v ss . dc operating conditions (ta = 0 to +70?c) parameter symbol min typ max unit notes supply voltage v cc , v ccq 2.3 2.5 2.7 v 1, 2 v ss , v ssq 000v input reference voltage v ref 1.15 1.25 1.35 v 1 termination voltage v tt v ref 0.04 v ref v ref + 0.04 v 1 dc input high voltage v ih v ref + 0.18 v ccq + 0.3 v 1, 3 dc input low voltage v il ?.3 v ref 0.18 v 1, 4 dc input signal voltage v in (dc) ?.3 v ccq + 0.3 v 5 dc differential input voltage v swing (dc) 0.36 v ccq + 0.6 v 6 notes: 1. all parameters are referred to v ss , when measured. 2. v ccq must be lower than or equal to v cc . 3. v ih is allowed to exceed v cc up to 4.6 v for the period shorter than or equal to 5 ns. 4. v il is allowed to outreach below v ss down to ?.0 v for the period shorter than or equal to 5 ns. 5. v in (dc) specifies the allowable dc execution of each differential input. 6. v swing (dc) specifies the input differential voltage required for switching.
hm5425161b, HM5425801B, hm5425401b series 43 dc characteristics (ta = 0 to +70?c, v cc , v ccq = 2.5 v 0.2 v, v ss , v ssq = 0 v) (hm5425161b) hm5425161b -75a -75b -10 parameter symbol min max min max min max unit test conditions notes operating current (actv-pre) i cc0 tbd tbd tbd ma cke 3 v ih , t rc = min 1, 2, 5 operating current (actv-read-pre) i cc1 tbd tbd tbd ma cke 3 v ih , bl = 2, cl = 2.5, t rc = min 1, 2, 5 idle power down standby current i cc2p tbd tbd tbd ma cke v il 4 idle standby current i cc2n tbd tbd tbd ma cke 3 v ih , cs 3 v ih 4 active power down standby current i cc3p tbd tbd tbd ma cke v il 3 active standby current i cc3n tbd tbd tbd ma cke 3 v ih , t ras = max 3 operating current (burst read operation) i cc4r tbd tbd tbd ma cke 3 v ih , bl = 2, cl = 2.5 1, 2, 5, 6 operating current (burst write operation) i cc4w tbd tbd tbd ma cke 3 v ih , bl = 2, cl = 2.5 1, 2, 5, 6 auto refresh current i cc5 tbd tbd tbd ma t rfc = min, input v il or 3 v ih self refresh current i cc6 2 2 2 ma input 3 v cc ?0.2 v input 0.2 v input leakage current i li ?0 10 ?0 10 ?0 10 m av cc 3 vin 3 v ss output leakage current i lo ?0 10 ?0 10 ?0 10 m av cc 3 vout 3 v ss output high voltage v oh v tt + 0.76 ? tt + 0.76 ? tt + 0.76 ?i oh (max) = ?5.2 ma output low voltage v ol ? tt 0.76 ? tt 0.76 ? tt 0.76 vi ol (min) = 15.2 ma notes. 1. these i cc data are measured under condition that dq pins are not connected. 2. one bank operation. 3. one bank active. 4. all banks idle. 5. command/address transition once per one cycle. 6. data/data mask transition twice per one cycle. 7. the i cc data on this table are measured with regard to t ck = min in general.
hm5425161b, HM5425801B, hm5425401b series 44 dc characteristics (ta = 0 to +70?c, v cc , v ccq = 2.5 v 0.2 v, v ss , v ssq = 0 v) (HM5425801B/hm5425401b) HM5425801B/hm5425401b -75a -75b -10 parameter symbol min max min max min max unit test conditions notes operating current (actv-pre) i cc0 tbd tbd tbd ma cke 3 v ih , t rc = min 1, 2, 5 operating current (actv-read-pre) i cc1 tbd tbd tbd ma cke 3 v ih , bl = 2, cl = 2.5, t rc = min 1, 2, 5 idle power down standby current i cc2p tbd tbd tbd ma cke v il 4 idle standby current i cc2n tbd tbd tbd ma cke 3 v ih , cs 3 v ih 4 active power down standby current i cc3p tbd tbd tbd ma cke v il 3 active standby current i cc3n tbd tbd tbd ma cke 3 v ih , t ras = max 3 operating current (burst read operation) i cc4r tbd tbd tbd ma cke 3 v ih , bl = 2, cl = 2.5 1, 2, 5, 6 operating current (burst write operation) i cc4w tbd tbd tbd ma cke 3 v ih , bl = 2, cl = 2.5 1, 2, 5, 6 auto refresh current i cc5 tbd tbd tbd ma t rfc = min, input v il or 3 v ih self refresh current i cc6 2 2 2 ma input 3 v cc ?0.2 v input 0.2 v input leakage current i li ?0 10 ?0 10 ?0 10 m av cc 3 vin 3 v ss output leakage current i lo ?0 10 ?0 10 ?0 10 m av cc 3 vout 3 v ss output high voltage v oh v tt + 0.76 ? tt + 0.76 ? tt + 0.76 ?i oh (max) = ?5.2 ma output low voltage v ol ? tt 0.76 ? tt 0.76 ? tt 0.76 vi ol (min) = 15.2 ma notes: 1. these i cc data are measured under condition that dq pins are not connected. 2. one bank operation. 3. one bank active. 4. all banks idle. 5. command/address transition once per one clock cycle. 6. data/data mask transition twice per one clock cycle. 7. the i cc data on this table are measured with regard to t ck = min in general.
hm5425161b, HM5425801B, hm5425401b series 45 capacitance (ta = 25 c, v cc , v ccq = 2.5 v 0.2 v) parameter symbol min max unit notes input capacitance (address) c i1 2.5 3.5 pf 1 input capacitance (command) c i2 2.5 3.5 pf 1 data and dos input/output capacitance (i/o) c o 4 5.5 pf 1, 2 notes: 1. these parameters are measured on conditions: f = 100 mhz, vout = v ccq /2, d vout = 0.2 v. 2. dout circuits are disabled.
hm5425161b, HM5425801B, hm5425401b series 46 ac characteristics (ta = 0 to +70?c, v cc , v ccq = 2.5 v 0.2 v, v ss , v ssq = 0 v) hm5425161b/hm542581b/hm5425401b -75a -75b -10 parameter symbol min max min max min max unit notes clock cycle time ( cas latency = 2) t ck 7.5 15 10 15 10 15 ns 10 ( cas latency = 2.5) t ck 7 15 7.5 15 8 15 ns input clock high level time t ch 0.45 0.45 0.45 t ck input clock low level time t cl 0.45 0.45 0.45 t ck clk to dqs skew t dqsck ?.7 0.7 ?.7 0.7 ?.8 0.8 ns 2 data to clk skew t ac ?.7 0.7 ?.7 0.7 ?.8 0.8 ns 2 dout to dqs skew t dqsq ?.5 0.5 ?.5 0.5 ?.6 0.6 ns 3 dout/dqs valid window t dv 0.35 0.35 0.35 t ck 4 dqs valid window t dqsv 0.35 0.35 0.35 t ck 4 dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck dout-high impedance delay from clk/ clk t hz ?.7 0.7 ?.7 0.7 ?.8 0.8 ns 5 dout-low impedance delay from clk/ clk t lz ?.7 0.7 ?.7 0.7 ?.8 0.8 ns 6 dq and dm input pulse width t dipw 1.7 1.7 2 ns 7 data and data mask to data strobe setup time t ds 0.5 0.5 0.6 ns 8 data and data mask to data strobe hold time t dh 0.5 0.5 0.6 ns 8 clock to dqs write preamble setup time t wpres 000ns clock to dqs write preamble hold time t wpreh 0.25 0.25 0.25 t ck dqs last edge to high-z time (dqs write postamble) t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 9 clock to the dqs first rising edge for write delay t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck
hm5425161b, HM5425801B, hm5425401b series 47 hm5425161b/HM5425801B/hm5425401b -75a -75b -10 parameter symbol min max min max min max unit notes dqs falling edge to clk setup time t dss 0.2 0.2 0.2 t ck dqs falling edge hold time to clk t dsh 0.2 0.2 0.2 t ck dqs high pulse width (dqs write) t dqsh 0.35 0.35 0.35 t ck dqs low pulse width (dqs write) t dqsl 0.35 0.35 0.35 t ck input command and address setup time t is 1.1 1.1 1.2 ns 8 input command and address hold time t ih 1.1 1.1 1.2 ns 8 active command period t rc 65 65 70 ns auto refresh to active/auto refresh command cycle t rfc 75 75 80 ns active to precharge command period t ras 45 120000 45 120000 50 120000 ns active to column command period t rcd 20 20 20 ns last data in to precharge t wr 15 15 15 ns precharge to active command period t rp 20 20 20 ns active to active command period t rrd 15 15 15 ns average periodic refresh interval t ref 7.8 7.8 7.8 m s
hm5425161b, HM5425801B, hm5425401b series 48 notes. 1. on all ac measurements, we assume the test conditions shown in the next page. for timing parameter definitions, see ?iming waveforms?section. 2. this parameter defines the signal transition delay from the cross point of clk and clk . the signal transition is defined to occur when the signal level crossing v tt . 3. the timing reference level is v tt . 4. output valid window is defined to be the period between two successive transition of data out or dqs (read) signals. the signal transition is defined to occur when the signal level crossing v tt . 5. t hz is defined as dout transition delay from low-z to high-z at the end of read burst operation. the timing reference is cross point of clk and clk . this parameter is not referred to a specific dout voltage level, but specify when the device output stops driving. 6. t lz is defined as dout transition delay from high-z to low-z at the beginning of read operation. this parameter is not referred to a specific dout voltage level, but specify when the device output begins driving. 7. input valid windows is defined to be the period between two successive transition of data input or dqs (write) signals. the signal transition is defined to occur when the signal level crossing v ref . 8. the timing reference level is v ref . 9. the transition from low-z to high-z is defined to occur when the device output stops driving. a specific reference voltage to judge this transition is not given. 10. t ck max is determined by the lock range of the dll. beyond this lock range, the dll operation is not assured. 11. v cc is assumed to be 2.5 v 0.2 v. v cc power supply variation per cycle expected to be less than 0.4 v/400 cycle.
hm5425161b, HM5425801B, hm5425401b series 49 test conditions parameter symbol min typ max unit input reference voltage v ref 1.15 1.25 1.35 v termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v ac input high voltage v ih (ac) v ref + 0.35 v ac input low voltage v il (ac) v ref - 0.35 v ac differential input high voltage v swing (ac) 0.7 v ccq + 0.6 v ac differential cross point voltage v x (ac) v ref - 0.2 v ref v ref + 0.2 v input signal slew rate slew 1 v/ns v tt v ref clk clk v ref v ss slew = (v ih (ac) ?v il (ac))/ d t measurement point v ih v il v cc v cc v ss dq r t = 25 w r s = 25 w c l = 30 pf v x d t t cl t ck t ch v swing
hm5425161b, HM5425801B, hm5425401b series 50 timing parameter measured in clock cycle number of clock cycle parameter symbol min max write to pre-charge command delay (same bank) t wpd 3 + bl/2 read to pre-charge command delay (same bank) t rpd bl/2 write to read command delay (to input all data) t wrd 2 + bl/2 burst stop command to write command delay ( cas latency = 2) t bstw 2 ( cas latency = 2.5) t bstw 3 burst stop command to dq high-z ( cas latency = 2) t bstz 2 ( cas latency = 2.5) t bstz 2.5 read command to write command delay (to output all data) ( cas latency = 2) t rwd 2 + bl/2 ( cas latency = 2.5) t rwd 3 + bl/2 pre-charge command to high-z ( cas latency = 2) t hzp 2 ( cas latency = 2.5) t hzp 2.5 write command to data in latency t wcd 1 write recovery t wr 2 dm to data in latency t dmd 0 register set command to active or register set command t mrd 2 self refresh exit to non-read command t snr 10 self refresh exit to read command t srd 200 power down entry t pden 1 power down exit to command input t pdex 1 cke minimum pulse width t ckepw 1
hm5425161b, HM5425801B, hm5425401b series 51 timing waveforms command and addresses input timing definition clk clk v ref command ( ras , cas , we , cs ) address t is t is t ih t ih
! "
! v ref read timing definition clk clk dqs high-z (v tt ) v tt v tt dq (dout) t lz t rpre t dqsck t ac t dv t hz t ck t ch/ t cl t cl/ t ch notes: 1. specific voltage for transition from/to high-z is not given. 2. the transition to high-z is defined to occur when output stop driving. 3. the transition from high-z is defined to occur when output begins driving. * 1 * 1 t dqsv t rpst t dqsv
hm5425161b, HM5425801B, hm5425401b series 52 write timing definition clk clk dqs dm v ref v ref v ref dq (din) t ds t dh t dqss t wpreh t wpres t ds t dh t dipw t dipw t dipw t ck t dsh t dss t dqsl t dqsh t wpst ! " # " # #
hm5425161b, HM5425801B, hm5425401b series 53 read cycle bank 0 active bank 0 read bank 0 precharge
5 < = '( / 6 7 = > ? 9 : 0 8 ? , 4 5 ; < ' / / 7 > ? ( 0 " # ) * 2 cas latency = 2 burst length = 4 bank0 access = v ih or v il bank 0 active bank 0 read bank 0 precharge ( 0 1 8
% & , - . 4 5 ' + , 3 4 : ; # $ $ % , - 4 & ' . / 5 6 =
: ) 1 8 9 8
! ( # * + 2 3 # . / 6 7 = > ) 0 1 2 9 2 9 : t is t ih t ch t ck t cl t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t rpre t rpst t dqsv t dqsv t dv t dv t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih ras a10 address high-z high-z cs cke clk clk cas we ba dqs, dqsu/dqsl dq (output) dm, dmu/dml v ih t rcd t ras t rp t rc
$ % + , 3 4 : ; b c j k l
hm5425161b, HM5425801B, hm5425401b series 54 write cycle bank 0 active 8 ? * 2 3 9 : $ % , - 3 4 ; < 7 ? - 5 6 < = " ) * 1 2 9 % , - 3 4 5 < % & - ' 0 1 8 9 cas latency = 2 burst length = 4 bank0 access = v ih or v il bank 0 active bank 0 write bank 0 precharge
& - . 6 # $ * + 1 2 3 : 8 9 " # * > ? ! " ( ) 0 1
3 ; < " # $ * + , 3
3 : ; < 0 78 ? . / 6 7 > 6 = > & ' . ! ( # $ + , 2 3 : ; & ' . / / 7 ? t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih v ih t rcd t ras t rc t rp t dqss t dqsl t dqsl t wpst t wr cs clk clk cke ras cas we ba a10 address dq (input) dm, dmu/dml dqs, dqsu/dqsl (input) t ck t ch t cl t ds t ds t ds t dh t dh t dh
hm5425161b, HM5425801B, hm5425401b series 55 mode register set cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clk clk cke cs ras cas we ba address dm, dmu/dml dq (output) 8 @ a i j
@ i < e f m n ; < d e l m 6 ? @ h 0 8 9 & ' $ % - 6 56 > g % - . 6 7 ? g 2 ; < c d k l % b valid code code t rp precharge if needed mode register set bank 3 active bank 3 read @ h i / 7 8 @ a i ' ( 0 ' ( 0 1 / 0 8 & / e f n o f o . / 6 7 @ & r: b c: b v ih bank 3 precharge t mrd high-z high-z % & cas latency = 2 burst length = 4 = v ih or v il dqs, dqsu/dqsl ! " & ' * . / 6 7 ? @ h p
hm5425161b, HM5425801B, hm5425401b series 56 read/write cycle % - . 6 ? g % . 6 7 ? h . 6 7 ? @ h 7 8 ? @ h i p o p " r:a c:a c:b r:b c:b'' " f o p & ' / 0 8 % & . & ' . / % & . / % . $ % - . 6 > g b?? bank 0 active bank 3 active bank 0 read bank 3 read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cke ras cs dqs, dqsu/dqsl cas we address clk ba dq (output) dq (input) clk bank 3 write t wrd high-z v ih t rwd b read cycle cas latency = 2 burst lenght = 4 =v ih or v il
dm, dmu/dml k ! " ) * 2 3 : ; c l a
hm5425161b, HM5425801B, hm5425401b series 57 auto refresh cycle $ % - . c k l ) * 2 3 ) * 1 2 : ; b c k . / 7 @ c l m l m : c k l $ % ! " ) * 1 2 3 : ; c
b c k l precharge if needed auto refresh bank 0 active bank 0 read clk clk cke cs cas we ba address dm, dmu/dml dq (output) dq (input) ras / 7 8 @ a 6 >? g o p
! " # cas latency = 2 burst length = 4 = v ih or v il v ih t rp a10=1 r: b c: b b high-z t rc dqs dqsu/dqsl
hm5425161b, HM5425801B, hm5425401b series 58 self refresh cycle & ' . / 6 7 ? @ h p self refresh entry self refresh exit high-z $ ,- 5 > m #$ , 4 5 < = e f m n % . $ & ' & ' ( / 0 8
$ , 4 5 = > e f m n p ( ) 0 1 8 9 b $ % d l m # clk cke cs ras cas we ba address dm, dmu/dml dq (output) dq (input) clk precharge if needed bank 0 active bank 0 read t rp t snr ' ( 0 e f n o h a10=1 r: b , 5 = > f / 0 c: b dqs dqsu/dqsl cas latency = 2.5 burst length = 4 = v ih or v il
$ t is t ih t ckepw cke = low
hm5425161b, HM5425801B, hm5425401b series 59 power down mode
# + , 4 5 < = e f m n p $ % . % & . / - . 6 7 ? gh p ! " $ - . 6 > f g o p $ ,- 5 = > e f n o
$

i j ' ( 0 ' ( 0 8 @ a h i " # + " # + . 7 ? @ h . 7 8 ? @ h i p . 7 8 ? @ h i p ' ' & / 8 & ' . / 7 8 & ' . / 7 8 # ' / 0 8 9 a high-z a10=1 r: c r: b clk cke cs ras cas we ba address dm, dmu/dml dq (output) dq (input) qs, qsu/qsl clk precharge if needed power down entry power down exit bank 0 active bank 0 read t pdex cas latency = 2.5 burst lenght = 4 =v ih or v il t pden cke = low t rp t is t ih t ckepw
hm5425161b, HM5425801B, hm5425401b series 60 package dimensions hm5425161btt/HM5425801Btt/hm5425401btt series (ttp-66d) hitachi code jedec eiaj weight (reference value) ttp-66d 0.53 g unit: mm *dimension including the plating thickness base material dimension 0.13 m 0.10 0.65 66 34 133 22.22 22.72 max 1.20 max 10.16 0.13 0.05 11.76 0.20 0 ?5 0.91 max *0.145 0.05 0.22 0.05 *0.24 0.07 0.125 0.04 0.50 0.10 0.68 0.80 preliminary
hm5425161b, HM5425801B, hm5425401b series 61 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
hm5425161b, HM5425801B, hm5425401b series 62 revision record rev. date contents of modification drawn by approved by 0.0 jun. 28, 1999 initial issue

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